With the increasing down-scaling of integrated circuits (IC) and increasingly demanding requirements to the speed of ICs, transistors need to have higher drive currents with increasingly smaller dimensions. Fin field-effect transistors (FinFET) were thus developed. In a typical finFET, portions of a substrate are etched away to create a vertical fin structure. This vertical fin structure is used to form source/drain regions in the lateral direction, forming a channel region in the fin. A gate is formed over the fin in the vertical direction forming a finFET.
In a typical IC finFET layout, a fin array (i.e., a group of fins) may be situated next to an empty region. Empty regions refer to portions of an IC device layer without any fins or other active components. The presence of empty regions near a fin array may create problems in subsequent process steps and even lead to process failures. For example, after fins are formed, photolithography techniques may be used to form other features in the IC (e.g., a gate). When a photo resist layer is placed over a fin array and an empty region, the photo resist may have uneven topography.
An uneven photo resist layer creates issues with focus during the photolithography process and may cause process failures. These issues may be particularly detrimental on the boundaries of the fin array because it impedes the formation of other features over the fin array. Therefore, it is desirable to minimize the presence of empty regions in an IC near a fin array.